MyVHDL Station V5.1

Description :
The "MyVHDL Station" is a tool to describe the desired Hardware's move ment or structure in VHDL (Very High speed IC Hardware Description Language) and verify it. The "MyVHDL Station" supports IEEE std 1076-1987 & 1993 VHDL language, the present standard VHDL, and enables us ers to verify not only Behavioral Description and Structural Description in VHDL, but also the mixed Description. Besides, the "MyVHDL Station"  perfectly supports the syntax indispensable to synthesis: the input of the "MySynthesis Station", a logic synthesis tool of VHDL syntax. In addition, by adopting the Compiled code methodology that enables users to interpr
et the design code and generate C-code so that they can effectively con duct verification of the pertinent design, the "MySynthesis Station" can conduct simulation faster than the previous version with the interpretive simulation methodology. Comparing to the other VHDL design tools, the advantages of the "MyVHDL Station" are as follows.
1) The upgrade of the "MyVHDL Station" persistently goes along with the performance-improvement work in a short time.
2) The library, which is suitable to the designing technique, is continuously provided.
The "MyVHDL Station" provides not only the Command input method that enables users to select the appropriate environment for the design verification but also the environment that enables users to conduct verification via GUI.     

Feature :
- Design a digital system using VHDL.
- Support the IEEE 1076-1987 VHDL Standard Library.
- Support the TextIO Library.
- Provide a verity of debugging information such as Wave, List, process, Structure, Signal, Variable, etc.
- Provide an easy-to-use VHDL Wizard and a VHDL Editor that supports both syntax Coloring and smart indentation.
- Support a VHDL Testbench Generator.


System Requirements :
Pentium-II or faster, memory 64MB or more, compatible with Windows 95/98/ME/2000