MBJ chips

*EDORAM4MEG x 16 or 16MEG x 4

* SDRAM

* Parallel Data Flash

* Serial Data Flash

Support external Data Memory :

* 1 Bulk Transfer Endpoint (Endpoint 3 OUT)

* 1 Bulk Transfer Endpoint (Endpoint 2 IN)

* 1 interrupt Endpoint (Endpoint 1 I / O)

* 1 Control Endpoint (Endpoint 0 I / O )

* Dual Data Pointer

* Enhance MUL instruction (one cycle)

* Two programmable full duplex UARTs 

* 2-Level interrupt priority structure

* Three 16-Bits internal Timers / Event counter

* 384 Bytes internal core-RAM

* One clock per machine cycle

* FOSC : 1 ~ 10 MHz oscillator         * LOSC : under 100 KHz oscillator