MFC700 sRIO VPX 32GB Integrated Circuits

Power and SCN Utility Signals (I2C)
4 sRIO x4s to Switch
RocketIO x4 from FPGA1
32 Differential Pairs or 64 Single Ended I/Os from J24
1 RS-232 with Handshake or 2 RS-232s from SCN
16 Differential Pairs or 32 Single Ended I/Os from SCN
32 Differential Pairs or 64 Single Ended I/Os from J14
1 x4 RocketIO Link from FPGA0
16 Differential Pairs with 2 Single Ended I/Os or
34 Single-Ended I/Os from SCN

Connectivity 
P0
P1
P2
P3
P4


P5
P6

 
 

 

Memory
The FPGA's primary function is as a memory controller. Two large DDR2 SDRAM memory banks connect to each FPGA. Each bank is 72-bits wide with 64-bits for data and 8-bits for ECC. The banks support from 1-4GB of memory, or 2-8GB per FPGA node. These banks run at 200MHz. By default, the board is supplied with a memory controller bitstream that supports sRIO and does not support User Programmable Logic (UPL).

12MB of FLASH for each FPGA node is available for storing bitstreams.

FPGA I/O
The FPGA nodes provide access to the sRIO fabric, RocketIO and low-speed I/O to satisfy a variety of applications. The FPGAs use a 3.125Gbps x4 link to connect to the sRIO switch. The FPGAs also include an advanced, corner-turning DMA engine. The sRIO switch links can be connected to other sRIO switches and endpoints, allowing the memory resources from the FPGA to be visible to all other parts of the system. The links support full-duplex transfers, enabling ping-pong transactions to the memory controllers or other I/Os of the device.

I/O capabilities for the FPGA nodes include RocketIO connections to the backplane, XMCs and between the FPGAs. A x4 link connects each FPGA to the backplane, using the P2 and P6 connectors. The RocketIOs can be used for protocols such as Aurora, Serial FPDP (sFPDP) or other high-speed serial interconnects (HSSI). RocketIO links between the FPGAs provide a low-overhead, high-speed connections where the FPGAs can compare data or do a transfer without going through sRIO. There are also x4 connections to the Jn5 XMC connectors.

The SCN provides low-speed I/Os to the FPGAs for applications where handling of system functions may be critical. The SCN acts like a switch, enabling transfers to pass to the other FPGAs or to go to the backplane.

System Control & Chassis Management
The onboard SCN controls chassis management, temperature monitoring, JTAG, bitstream encryption and routing of single ended I/Os. Users can take advantage of Curtiss-Wright's default HDL functionality or program their own logic into the SCN. The SCN has 128MB of local DDR2 available for quick loading of bitstreams using a 16-bit bus. Another 4MB of FLASH is available for storing FPGA images. The SCN's ability to function as a switch for Single Ended I/Os can be seen in the SCN I/Os diagram.

Mezzanine Sites
The MFC700 includes two XMC (VITA 42) mezzanine sites. Each site can connect to the sRIO switch, as well as directly to the coupled FPGA node. This gives users the capability to access the sRIO fabric, specifically with the MM-6171 Buffer Memory XMC module with up to 2-8GB of memory. The MFC700 with two MM-6171s provides up to 32GB of memory per slot (16GB on the MFC700 baseboard and 8GB per mezzanine site).

The MFC700 is a 6U VPX-REDI memory carrier with support for up to 16GB of memory on the baseboard, dual XMC mezzanine sites and a Serial RapidIO (sRIO) fabric. Designed for applications that buffer large amount of high-speed data, the card can be utilized in signal and image processing applications, as well as snapshot and recording subsystems. The dual XMC mezzanine sites provide flexibility for system expansion, specifically for adding additional memory XMCs boosting the total memory capacity to 32 GB.

6U VPX-REDI 32GB Memory FPGA XMC Carrier with Serial RapidIO