FPE650 VPX Quad Virtex-5 FPGA Integrated Circuits

Digital Receiver
The combination of processor performance, high bandwidth, interchangeable FMC module for analog I/O and Curtiss-Wright FPGA IP make the FPE650 an ideal digital receiver platform. Ideal applications include Signal Intelligence (SigInt), Software Defined Radio and Radar applications.

Xilinx Virtex-5 FPGA Nodes
The four SX95T FPGAs are closely coupled for multiple banks of QDR2 SRAM and DDR2 SDRAM (depending on FPGA site) for increased system performance. The FPGAs are inter-connected through a network of x4 RocketIO links and parallel connections for high bandwidth, low latency data communications. There are dedicated high speed links that connect to the front panel FMC sites and VPX backplane connections.

FMC Sites
Two FPGAs are connected to an FPGA Mezzanine Card (FMC) site. FMC is defined by the VITA 57 specification as a mezzanine format designed to take advantage of FPGA based I/O - high bandwidth, reduced latency, simplified design and lower cost. FMCs do not require CPU busses such as PCI and consequently all control and flexibility is embodied within the FPGA directly. The FPE650 provides 68 differential parallel FPGA links to each site, a x4 full duplex RocketIO link and an Ethernet port. A zero latency cross bar switch is used to determine how the FMC x4 RocketIO link is used thereby providing a flexible solution.

VPX/VPX-REDI
ANSI/VITA 46.0-2007 provides a large number of high speed serial data links and ideal for FPGA solutions. Dual x4 links to all FPGAs are made available to the backplane for high bandwidth communications to the VPX backplane. There are additional x4 links, via a cross bar switch on the FPE650, and parallel backplane connections to two FPGAs increase I/O and system bandwidth further.

Commercial air-cooled, rugged air-cooled and conduction-cooled variants are also available compliant to the VPX-REDI mechanical format. The default board pitch is 1".

Configuration Control Processor (CCP)
Embedded within the FPE650 is a CCP. This has two roles: to configure the FPGAs via FLASH or SDRAM and to setup up the cross bar switch. The CCP is accessed by an HTML browser attached to front or backplane Ethernet connections.

Software/HDL Support
The FPE650 is a pure FPGA board and intended to be used alongside a CPU system controller. Sophisticated HDL examples are provided such as DMA driven memory interfaces, FMC sites and network connected FPGAs. JTAG headers are provided for application development using ChipScope tools. Support is provided for the Xilinx ISE toolchain.