TMS320LF2403APAGA IC

High-Performance Static CMOS Technology
25-ns Instruction Cycle Time (40 MHz)
40-MIPS Performance
Low-Power 3.3-V Design
- Based on TMS320C2xx DSP CPU Core
Code-Compatible With F243/F241/C242
Instruction Set and Module Compatible
With F240/C240
- Flash (LF) and ROM (LC) Device Options
LF240xA: LF2407A, LF2406A,
LF2403A, LF2402A
LC240xA: LC2406A, LC2404A,
LC2403A, LC2402A
- On-Chip Memory
Up to 32K Words x 16 Bits of Flash
EEPROM (4 Sectors) or ROM
Programmable Code-Security Feature
for the On-Chip Flash/ROM
Up to 2.5K Words x 16 Bits of
Data/Program RAM
544 Words of Dual-Access RAM
Up to 2K Words of Single-Access RAM
- Boot ROM (LF240xA Devices)
SCI/SPI Bootloader
- Up to Two Event-Manager (EV) Modules
(EVA and EVB), Each Includes:
Two 16-Bit General-Purpose Timers
Eight 16-Bit Pulse-Width Modulation
(PWM) Channels Which Enable:
Three-Phase Inverter Control
Center- or Edge-Alignment of PWM
Channels
Emergency PWM Channel Shutdown
With External PDPINTx Pin
Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults
Three Capture Units for Time-Stamping
of External Events
Input Qualifier for Select Pins
On-Chip Position Encoder Interface
Circuitry
Synchronized A-to-D Conversion
Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control
Applicable for Multiple Motor and/or
Converter Control

TMS320LF2403APAGA, DSP CONTROLLERS