FPE320 VPX Virtex-5 FPGA Integrated Circuits

Priority Signature Support is available for this product.  See the Technical Support fact sheet for details.

FusionXF FPGA Development Kit
The FPE320 uses the FusionXF FPGA Development Kit to speed HDL development and to communicate with processors and other FPGAs in a system. FusionXF provides FPGA Hardware Development Logic (HDL) functions, application APIs, drivers, and utilities to simplify the task of integrating FPGAs into an embedded real-time DSP system design. It aids customers in the development of their FPGA algorithms and logic for our customer- programmable FPGA products by providing all the building blocks to build a fully functional FPGA design to which a customer can integrate their FPGA logic and algorithms. FusionXF also provides mechanisms for communication between FPGAs as well as communication between FPGAs and processors. It includes example designs that show how to implement common FPGA functions such as control registers, DMA engines, interrupts, etc. and how to control these functions and communicate with them from software.
 

Mezzanine Site
The FPE320 includes a versatile set of I/O options through a FPGA Mezzanine Card (FMC) mezzanine site (VITA 57). FMCs provides fl exibility for the latest I/O such as A/D converters, SerialFPDP (sFPDP), LVDS, and others, and can also be designed by customers by following the VITA 57 standard.

System Control & Chassis Management
The on-board SCN controls chassis management, temperature monitoring, JTAG, bitstream encryption, and routing of single ended I/Os.

FPGA I/O
The FPGA node on the FPE320 has a tremendous amount of  I/O resources for connecting to other parts of the system. In terms of RocketIO high-speed serial links, the FPGA compute node utilizes up to 20 RocketIOs depending on which package is used. For the larger devices, such as LX330T and SX240T 20 links are used. These links are divided between I/O to FMC and to the backplane. Parallel I/O is also used, with up to 164 lines routed to the dedicated FMC site, and 38 single-ended I/Os or 18 differential pairs and 2 single-ended I/Os routed to the SCN.

Memory
The memory resources on each FPGA node of the FPE320 gives users the ability to process and store data sets for the most demanding applications. Each FPGA node has both DDR2 and QDR-II SRAM available. The DDR2 is organized into two banks, with each bank providing a x32 bus width using two x16 devices. Up to 512MB of memory is available from each DDR2 bank, providing a large amount of storage space for data sets. Complementing the DDR2 for more processing intensive tasks are two independent banks of QDR-II SRAM banks. The banks each have a x36 bus width, and provide immense bandwidth as they are quad data rate. The QDR-II banks do not need to track addressing because they are SRAMs, shortening development time for the user. Each bank is 9MB, for a total of 18MB available from each FPGA. 12MB of FLASH is available for storing bitstreams, although they can also be loaded through the System Controller Node (SCN).

With over 330,000 logic cells, the LX330T gives FPGA designers the most amount of space to program their algorithm. With 1,056 DSP slices and over 240,000 logic cells, the SXT device is ideal for A/D projects where the DSP48E slices can be used to maximum benefit.

The FPE320 supports Xilinx Virtex-5 LXT, SXT devices. Using the L220XT or LX330T for logic-intensive applications, the SX240T for DSP applications, and the FXT for all-around performance, developers can tailor their hardware resources to match their algorithm needs. 

Xilinx Virtex-5 3U VPX Processor with FMC Site