The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the clock signal once the initial starting address has been specified.
The device incorporates an internal address counter that automatically increments on every
clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each
opcode depends on the maximum clock frequency that will be used to read data from the
device. The 0Bh opcode can be used at any clock frequency up to the maximum specified by
fCLK, and the 03h opcode can be used for lower frequency read operations up to the maximum
specified by fRDLF.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate
opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the
three address bytes must be clocked in to specify the starting address location of the first byte to
read within the memory array. Following the three address bytes, an additional dummy byte
needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output
with the MSB of a byte first. When the last byte (03FFFFh) of the memory array has been read,
the device will continue reading back at the beginning of the array (000000h). No delays will be
incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance
state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
Figure 7-1. Read Array - 0Bh Opcode
Figure 7-2. Read Array - 03h Opcode
SCK
CS
SI
SO
MSB MSB
0 1 2 3
0 0 0 0 1 0 1 1
4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
OPCODE
A A A A A A A A A
MSB
X X X X X X X X
MSB MSB
D
IC AT90s |
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