54pin TSOP
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
Burst read single-bit write operation
DQM (x8) & L(U)DQM (x16) for masking
Auto & self refresh
64ms refresh period (4K cycle)
Pb/Pb-free Package
RoHS compliant for Pb-free Package
Feature:
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54pin TSOP JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the ...
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FEATURES 1.8V power supply, 1.8V I/O power Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation 1 /CS 1 CKE Differential clock inputs(CK and CK) MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst ...