Four CAS lines, four WE lines, and one OE line
DRAM controller programmable to support most size and speed memory interfaces
Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
Up to 30 wait states programmable per memory bank
Each bank can be a chip select or RAS to support a DRAM bank.
Contains complete dynamic RAM (DRAM) controller
Memory controller (eight banks)
32 address lines
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
Advanced on-chip emulation debug mode
and 16 protection groups
MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces
MMUs with 32-entry TLB, fully associative instruction and data TLBs
are lockable on a cache block basis.
Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and
blocks.
Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
Data cache is two-way, set-associative with 256 sets
Instruction cache is two-way, set-associative with 256 sets in 2 blocks
8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)
The core performs branch prediction with conditional prefetch and without conditional execution.
general-purpose registers (GPRs)
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit
The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.
The 133-MHz core frequency supports 2:1 mode only.
Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
Embedded MPC8xx core up to 133 MHz
The following list summarizes the key MPC875/870 features:
integration unit (SIU), and a communications processor module (CPM).
The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system
Features
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IC MPC870ZT66 MPC870ZT MPC870Z MPC870 - Hardware Specifications - Freescale Semiconductor, Inc
Model Number: | MPC870ZT66 |